1. Field of the Invention
The present invention relates to a method for forming capacitor, and more particularly to a method that improves quality of capacitor by annealing dielectric layer before metal interconnect is formed.
2. Description of the Prior Art
Capacitors are used extensively in electronic devices for storing electric chargers. Applications of capacitors comprise memories, filters, analog-to-digital converters and various control devices. The capacitors essentially comprise two conductive plates and an insulator that locates between two conductive plates. Moreover, the capacitance, or amount of charges held by the capacitor per applied voltage, is measured in farads and depends upon the area of the conductive plates, the distance between conductive plates and the dielectric value (K) of the insulator.
The material of conductive plates of capacitor comprises polysilicon, polycide and metal. Polysilicon is conventional material but metal plate is a current trend for quality of capacitor with metal plate is better than conventional capacitor with polysilicon plate. In current metal-insulator-metal capacitor, bottom plate of capacitor is widespread either provided by a metal layer or is formed on a metal layer. Where metal layer is used to form metal interconnect and material of metal layer comprises Al and Cu. Beside, insulator layer is widespread provided by a dielectric layer, especially by a high K dielectric layer.
Obviously, for conventional metal-insulator-metal capacitor as FIG. 1 shows. First, a plurality of metal interconnects 11 are formed on substrate 10, where material of metal interconnects 11 comprises Al and Cu. Second, bottom plate 12, dielectric layer 13 and top plate 14 are formed on one interconnect 11 in sequence to form the metal-insulator-metal capacitor, where leakage current and breakdown voltage of dielectric layer 13 is improved by annealing process. Beside, substrate 10 is covered by inter-layer dielectric 15, and vias 16 are formed to connect interconnects 11 and the metal-insulator-metal capacitor. Moreover, surface of inter-dielectric layer 15 is planarized and a plurality of second interconnects 17 are formed on the surface. Of course, sometime bottom plate 12 is provided by one metal interconnect 11.
Obviously, there is a serious drawback that metal interconnects 11 are formed before formation of dielectric layer 13. Because quality of dielectric layer 13 is improved by annealing but quality of metal interconnects 11 is degraded by thermal treatment, it is impossible to acquire both good metal interconnects 13 and good metal-insulator-metal capacitor.
Obviously, when integration of integrated circuit is increased, areas of bottom plate 12 and top plates 14 are diminished. Then previous drawback is more serious for capacitance of capacitor can not be enhanced by annealing dielectric layer 13 to increase dielectric value of dielectric layer 13.
It should be noted that previous drawback not only is serious for metal capacitor, it is serious for any capacitor that dielectric layer is formed after metal line.
According to previous discussion, it is crystal-clear that in order to increase capacitance of capacitor and forms both high capacitance capacitor and low resistance metal interconnect. It is desired to develop a method that overcomes the drawback that dielectric layer can not be improved by annealing for surrounding metal interconnect is degraded by annealing.